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rev. 1.0 5/12 copyright ? 2012 by silicon laboratories SI514 SI514 a ny -f requency i 2 c p rogrammable xo (100 kh z to 250 mh z ) features applications description the SI514 user-programmable i 2 c xo utilizes silicon laboratories' advanced pll technology to provide any frequency from 100 khz to 250 mhz with programming resolution of 0.026 parts per billion. the SI514 uses a single integrated crystal and silicon labs? proprietary dspll synthesiz er to generate any frequency across this range using simple i 2 c commands. ultra-fine tuning resolution replaces dacs and vcxos with an all-digital pll solution that improves performance where synchronization is necessary or in free-running reference clock applications. this solution provides superior supply noise rejection, simplifying low jitter clock generation in noisy environments. crystal esr and dld are individually production-tested to guarantee pe rformance and enhance reliability. the SI514 is factory-configurable for a wide variety of user specifications, including startup frequency, i 2 c address, supply voltage, output format, and stability. specific configurations are factory- programmed at time of shipment, eliminating long lead times and non-recurring engineering charges associated with custom frequency oscillators. functional block diagram ? programmable to any frequency from 100 khz to 250 mhz ? 0.026 ppb frequency tuning resolution ? glitch suppression on oe, power on and frequency transitions ? low jitter operation ? 2- to 4-week lead times ? total stability includes 10-year aging ? comprehensive production test coverage includes crystal esr and dld ? on-chip ldo for power supply noise filtering ? 3.3, 2.5, or 1.8 v operation ? differential (lvpecl, lvds, hcsl) or cmos output options ? optional integrated 1:2 cmos fanout buffer ? industry standard 5 x 7 and 3.2x5mm packages ? ?40 to 85 o c operation ? all-digital plls ? dac+ vcxo replacement ? sonet/sdh/otn ? 3g-sdi/hd-sdi/sdi ? datacom ? industrial automation ? fpga/asic clock generation ? fpga synchronization ordering information: see page 28. pin assignments: see page 27. si5602 1 2 3 6 5 4 gnd scl v dd clk+ clk? sda
SI514 2 rev. 1.0
SI514 rev. 1.0 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 2.1. programming a new output frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2. programming a small frequency change (sub 1000 ppm) . . . . . . . . . . . . . . . . . . 13 2.3. programming a large frequency change (> 1000 ppm) . . . . . . . . . . . . . . . . . . . . 14 3. all-digital pll applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 4. user interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2. register detailed descripti on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.3. i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5.1. dual cmos (1:2 fanout buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 7. package outline diagram: 5 x 7 mm, 6- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8. pcb land pattern: 5 x 7 mm, 6- pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 9. package outline diagram: 3. 2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10. pcb land pattern: 3.2 x 5.0 mm, 6-pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 11. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 11.1. SI514 top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 11.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
SI514 4 rev. 1.0 1. electrical specifications table 1. operating specifications v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units supply voltage v dd 3.3 v option 2.97 3.3 3.63 v 2.5 v option 2.25 2.5 2.75 v 1.8 v option 1.71 1.8 1.89 v supply current i dd cmos, 100 mhz, single-ended ?2126ma lvds (output enabled) ?1923ma lvpecl (output enabled) ?3943ma hcsl (output enabled) ?4144ma tristate (output disabled) ??18ma operating temperature t a ?40 ? 85 o c table 2. input characteristics v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units sda, scl input voltage high v ih 0.80 x v dd ??v sda, scl input voltage low v il ? ? 0.20 x v dd v
SI514 rev. 1.0 5 table 3. output clock frequency characteristics v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units programmable frequency range f o cmos, dual cmos 0.1 ? 212.5 mhz f o lvds/lvpecl/hcsl 0.1 ? 250 mhz frequency reprogramming resolution m res ? 0.026 ? ppb frequency range for small frequency change (continuous glitchless output) from center frequency ?1000 ? +1000 ppm settling time for small frequency change <1000 ppm from center frequency ? ? 100 s settling time for large frequency change (out- put squelched during fre- quency transition) >1000 ppm from center frequency ??10ms total stability* frequency stability grade c ?30 ? +30 ppm frequency stability grade b ?50 ? +50 ppm frequency stability gr ade a ?100 ? +100 ppm temperature stability f requency stability grade c ?20 ? +20 ppm frequency stability grade b ?25 ? +25 ppm frequency stability grade a ?50 ? +50 ppm startup time t su minimum v dd until output frequency (f o ) within specification ??10ms disable time t d f o < 10 mhz ? ? 40 s f o ? 10 mhz ? ? 5 s enable time t e f o < 10 mhz ? ? 60 s f o ? 10 mhz ? ? 20 s *note: total stability includes initial accuracy, operating temper ature, supply voltage change, load change, shock and vibration (not under operati on), and 10 years aging at 40 o c.
SI514 6 rev. 1.0 table 4. output clock levels and symmetry v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c parameter symbol test condition min typ max units cmos output logic high v oh 0.85 x v dd ??v cmos output logic low v ol ? ? 0.15 x v dd v cmos output logic high drive i oh 3.3 v ?8 ? ? ma 2.5 v ?6 ? ? ma 1.8 v ?4 ? ? ma cmos output logic low drive i ol 3.3 v 8 ? ? ma 2.5 v 6 ? ? ma 1.8 v 4 ? ? ma cmos output rise/fall time (20 to 80% v dd ) t r /t f 0.1 to 125 mhz, c l = 15 pf ?0.81.2ns 0.1 to 212.5 mhz, c l = no load ?0.60.9ns lvpecl/hcsl out- put rise/fall time (20 to 80% v dd ) t r /t f ??565ps lvds output rise/fall time (20 to 80% v dd ) t r /t f ??800ps lvpecl output com- mon mode v oc 50 ? to v dd ? 2 v, single-ended ? v dd ? 1.4 v ?v lvpecl output swing v o 50 ? to v dd ? 2 v, single-ended 0.55 0.8 0.90 v ppse lvds output common mode v oc 100 ? line-line, 3.3/2.5 v 1.13 1.23 1.33 v 100 ? line-line, 1.8 v 0.83 0.92 1.00 v lvds output swing v o single-ended 100 ?? differential termination 0.25 0.35 0.45 v ppse hcsl output common mode v oc 50 ?? to ground 0.35 0.38 0.42 v hcsl output swing v o single-ended 0.58 0.73 0.85 v ppse duty cycle dc 485052%
SI514 rev. 1.0 7 table 5. output clock jitter and phase noise (lvpecl) v dd = 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvpecl parameter symbol test condition min typ max units period jitter (rms) jprms 10 k samples 1 ??1.3ps period jitter (pk-pk) jppkpk 10 k samples 1 ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ? 0.31 0.5 ps 12 khz to 20 mhz integration bandwidth 2 ?0.81.0ps phase noise, 156.25 mhz n 100 hz ? ?86 ? dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz additive rms jitter due to power supply noise 3 jpsr 10 khz sinusoidal noise ? 3.0 ? ps 100 khz sinusoidal noise ? 3.5 ? ps 500 khz sinusoidal noise ? 3.5 ? ps 1 mhz sinusoidal noise ? 3.5 ? ps spurious spr lvpecl output, 156.25 mhz, offset > 10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz. 3. 156.25 mhz. increase in jitter on output clock due to sinewave noise added to vdd (2.5/3.3 v = 100 mvpp).
SI514 8 rev. 1.0 table 6. output clock jitter and phase noise (lvds) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = lvds parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples 1 ??2.1ps period jitter (pk-pk) jppkpk 10k samples 1 ??18ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.55ps 12 khz to 20 mhz integration bandwidth 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?109 ? dbc/hz 10 khz ? ?116 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5, 250 mhz. 2. applies to output frequencies: 100 , 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 and 250 mhz.
SI514 rev. 1.0 9 table 7. output clock jitter and phase noise (hcsl) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = hcsl parameter symbol test condition min typ max unit period jitter (rms) jprms 10k samples * ??1.2ps period jitter (pk-pk) jppkpk 10k samples * ??11ps phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth * (brickwall) ?0.250.30ps 12 khz to 20 mhz integration band- width * (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??90?dbc/hz 1khz ? ?112 ? dbc/hz 10 khz ? ?120 ? dbc/hz 100 khz ? ?127 ? dbc/hz 1 mhz ? ?140 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc *note: applies to an output frequency of 100 mhz.
SI514 10 rev. 1.0 table 8. output clock jitter and phase noise (cmos, dual cmos) v dd = 1.8 v 5%, 2.5 or 3.3 v 10%, t a = ?40 to +85 o c; output format = cmos, dual cmos parameter symbol test condition min typ max unit phase jitter (rms) j 1.875 mhz to 20 mhz integration bandwidth 2 (brickwall) ?0.250.35ps 12 khz to 20 mhz integration bandwidth 2 (brickwall) ?0.81.0ps phase noise, 156.25 mhz n100hz ??86?dbc/hz 1 khz ? ?108 ? dbc/hz 10 khz ? ?115 ? dbc/hz 100 khz ? ?123 ? dbc/hz 1 mhz ? ?136 ? dbc/hz spurious spr lvpecl output , 156.25 mhz, offset>10 khz ??75?dbc notes: 1. applies to output frequencies: 74.17 582, 74.25, 75, 77.76, 100, 106.25, 125, 148.35165, 148.5, 150, 155.52, 156.25, 212.5 mhz. 2. applies to output frequencies: 100, 106.25, 1 25, 148.35165, 148.5, 150, 15 5.52, 156.25, 212.5 mhz. table 9. environmental compliance and package information parameter conditions/test method mechanical shock mil-std-883, method 2002 mechanical vibration mil-std-883, method 2007 solderability mil-std -883, me thod 2003 gross and fine leak mil-std-883, method 1014 resistance to solder heat mil-std-883, method 2036 moisture sensitivity level msl 1 contact pads gold over nickel
SI514 rev. 1.0 11 table 10. thermal characteristics parameter symbol test condition value units thermal resistance junction to ambient * ? ja still air 110 c/w *note: applies to 5 x 7 and 3.2 x 5 mm packages. table 11. absolute maximum ratings 1 parameter symbol rating units maximum operating temperature t amax 85 o c storage temperature t s ?55 to +125 o c supply voltage v dd ?0.5 to +3.8 v input voltage (any input pin) v i ?0.5 to v dd + 0.3 v esd sensitivity (hbm, per jesd22-a114) hbm 2 kv soldering temperature (pb-free profile) 2 t peak 260 o c soldering temperature time at t peak (pb-free profile) 2 t p 20?40 sec notes: 1. stresses beyond those listed in this table may cause pe rmanent damage to the device. functional operation or specification compliance is not impli ed at these conditions. exposure to ma ximum rating conditions for extended periods may affect device reliability. 2. the device is compliant with jedec j-std-020.
SI514 12 rev. 1.0 2. functional description the SI514 offers system designers a programmable, low jit ter xo solution with exceptionally fine frequency tuning resolution. to enable designers to ta ke full advantage of this flexibility and performance, s ilicon laboratories provides an easy-to-use evaluation kit and intuitive suite of wi ndows-based software utilit ies to simplify the SI514 programming process. the si5xx-prog-evb kit contains th e programmable oscillator software suite and an evb driver (usbxpress ? ) for use with usb-equipped pcs. go to http://www.silabs.com/products/clockso scillators/pages/de velopmenttools.aspx for more information. alternatively, ?2.1. programming a new output frequency? provides designers a detailed description, along with examples, of the frequency programming requirements and process for designers who are interested in learning more about the programmi ng algorithms implemented within the progra mmable oscillator software suite. 2.1. programming a new output frequency the output frequency (fout) is determined by programming the feedback multiplier (m=m_int.m_frac), high- speed divider (hs_div), and low- speed divider (ls_div) according to the following formula: figure 1. block diagram of SI514 the value of the feedback multiplier m is adjustable in the following range: ? 65.04065041 ? m ? 78.17385866. this keeps the vco frequency within the range of 2080 mhz ? f vco ? 2500 mhz, since the vco frequency is the product of the internal fixed-frequency crystal (f xo ) and the high-resolution 29-bit fractional multiplier (m). this 29- bit resolution of m allows the vc o frequency to have a frequency tuning resolution of 0.026 ppb. the device comes from the factory with a pre-programmed center frequency within the range of 100 khz ?? f out ?? 250 mhz, as specified by the 6-digit code in the part number. (see section ?6. ordering information? for more information.) to change from the fa ctory-programmed frequency to a different value, the user must follow one of two algorithms based on the magnitude of the frequency change. ? ?small frequency change.? to change the frequency by < 1000 ppm, the user must keep the same center frequency and only update the value of m. refer to section "2.2. programming a small frequency change (sub 1000 ppm)" on page 13. ? ?large frequency change.? to change the frequency by ?? 1000 ppm, the user must change the center frequency. this may require updates to the output divi ders (hs_div and/or ls_div) and possibly the lp1 and f out f xo m ? hs_div ls_div ? ------------------------------------------------- - where f xo 31.98mhz = =
SI514 rev. 1.0 13 lp2 values, in addition to updating the value of m, which requires the vco to be reca librated. refer to section "2.3. programming a large frequency change (> 1000 ppm)" on page 14. figure 2 provides a graphic depiction of the difference between small and large frequency changes. figure 2. small vs. large frequency change illustration 2.2. programming a small fr equency change (sub 1000 ppm) the value of the feedback multiplier, m is the only parameter that needs to be updated for output frequency changes less than 1000 ppm from the center frequency (recalibrating the vco is not required). this enables the output to remain continuous during the change. for example, the output frequency can be swept continuously between 148.5 mhz and 148.352 mhz (i.e., ?0.997 ppm) with no output discontinuities or glitches by changing m in either multiple steps or in a single step. for small frequency changes, each update of m requires 100 s to settle. note: it is not possible to implement a frequency change 1000 ppm using multiple small frequency changes without changing the center frequen cy and recalibrating the vco. use the following procedure to make small frequency changes: 1. if the current value of m is already known, then skip to step 2; else, using the serial port, read the current m value (registers 5-9). 2. calculate the new value of m as follo ws (all values are in decimal format): a. mcurrent = m_int + m_frac/2 29 (eq 2.2) b. mnew = mcurrent x f out _new / f out _current (eq 2.3) c. m_intnew = int[mnew]* (eq 2.4) d. m_fracnew = (mnew ? int[mnew]) x 2 29 (eq 2.5) *where int[n] rounds n down to the nearest integer (e.g., int[3.9] = 3) 3. using the i 2 c port, write the new value of m_frac[23:0] (not all registers need to be updated.) (registers: 5, 6, 7) 4. if necessary, write new value of m_int[2:0] and m_frac[28:24] re gister. (register 8) 5. write m_int[8:3]. (register 9) frequency chan ges take effect when m_int[8:3] is written. example 2.1: an SI514 generating a 148.5 mhz clock must be reconfigur ed ?on-the-fly? to generate a 148.352 mhz clock. this represents a change of ?0.996.633 ppm which is within the 1000 ppm window. 1. read the current value of m: a. register 5 = 0xd3 (m_frac[7:0]) b. register 6 = 0x65 (m_frac[15:8]) c. register 7 = 0x7c (m_frac[23:16]) f vco_min (2080 mhz) f vco_max (2500 mhz) range of small frequency change programming a new center frequency requires a vco calibration and the output should be squelched f center f' center small frequency change large frequency change f center +1000 ppm f center -1000 ppm
SI514 14 rev. 1.0 d. register 8 = 0x49 (m_int[2:0],m_frac[28:24]) e. register 9 = 0x09 (m_int[8:3]) f. m_int = 0b001001010 = 0x4a = 0d74 g. m_frac = 0x097c65d3 = 159,147,475 h. m= m_int + m_frac/2 29 = 74 + 159,147,475/2 29 = 74.296435272321105 2. calculate mnew: a. mnew = 74.296435272321105 x 148.352/148.5 = 74.2223889933965 b. m_intnew = 74 = 0x4a c. m_fracnew = 0.2223889933965 x 2 29 = 119,394,181 = 0x071dcf85 3. write mnew to registers 5-7: a. register 5 = 0x85 b. register 6 = 0xcf c. register 7 = 0x1d 4. write mnew to register 8: a. register 8 = 0x47 5. write mnew to register 9: a. register 9 = 0x09 2.3. programming a large fr equency change (> 1000 ppm) large frequency changes are those that vary the f vco frequency by an amount greater than 1000 ppm from an operating f center . figure 2 illustrates the difference between la rge and small frequency changes. changing from f center to f' center requires a calibration cycle that rese ts internal circuitry to establish f' center as the new operating center frequency. the below steps are recommended when performing large frequency changes: 1. disable the output: write oe register bit to a 0 (register 132, bit2) 2. if using one of the standard frequencies listed in t able 12, then write the new lp1, lp2, m_frac, m_int, hs_div and ls_div register values according to the table (be sure to write m_int[8:3] (register 9) after writing to the m_frac registers (registers 5-8)). skip to step 9. if the desired frequency is not in the table, then follow steps 4-8 below. 3. determine the minimum value of ls_d iv (minimizing ls_div minimizes the number of dividers on the output stage, thus minimizing jitter) according to the following formula: a. ls_div = f vco (min)/(f out x hs_div(max)) (eq 2.6) b. ls_div = 2080/(f out (mhz) x 1022) (eq 2.7) i. since ls_div is restricted to: dividing by 1,2, 4,8,16,32, choose the next largest value over the result derived in eq 2.7 (e.g., if result is 4.135, choose ls_div = 8) 4. determine the minimum value for hs_div (this optimizes timing margins) a. hs_div(min) = f vco (min)/(f out x ls_div) (eq 2.8) b. hs_div(min) = 2080/(f out (mhz) x ls_div) (eq 2.9) i.hs_div(min) will be the next even number greater than or equal to the result derived in eq 2.9 (keeping in the range of 10-1022) note: speed_grade_min (reg 48) ls_div x hs_div speed_grade_max (reg 49); if outside this range, the output will be forced to the disabled state. 5. determine a value for m according to the follo wing formula (all values are in decimal format): a. m = ls_div x hs_div x f out /f xo (eq 2.10) b. m = ls_div x hs_div x f out (mhz)/31.98 (eq 2.11) c. m_int = int[m] (eq 2.12) d. m_frac = (m ? int[m]) x 2 29 (eq 2.13)
SI514 rev. 1.0 15 table 12. standard frequency table dec hex fout (mhz) m m_int m_frac hsdiv lsdiv lp1 lp2 m_intx m_fracx hsdivx lsdivx lp1_x lp2_x 0.100000 65.04065041 65 21824021 650 5 2 2 41 14d0215 28a 5 2 2 1.544000 65.08167605 65 43849494 674 1 2 2 41 29d1716 2a2 1 2 2 2.048000 65.06466542 65 34716981 1016 0 2 2 41 211bd35 3f8 0 2 2 4.096000 65.06466542 65 34716981 508 0 2 2 41 211bd35 1fc 0 2 2 4.915200 65.16712946 65 89726943 424 0 2 2 41 5591fdf 1a8 0 2 2 19.440000 65.65103189 65 349520087 108 0 2 3 41 14d540d7 6c 0 2 3 24.576000 66.08930582 66 47945695 86 0 2 3 42 2db97df 56 0 2 3 25.000000 65.66604128 65 357578187 84 0 2 3 41 155035cb 54 0 2 3 27.000000 65.85365854 65 458304437 78 0 2 3 41 1b512bb5 4e 0 2 3 38.880000 65.65103189 65 349520087 54 0 2 3 41 14d540d7 36 0 2 3 44.736000 67.14596623 67 78365022 48 0 2 3 43 4abc15e 30 0 2 3 54.000000 67.54221388 67 291098862 40 0 2 3 43 1159d0ee 28 0 2 3 62.500000 66.44777986 66 240399983 34 0 2 3 42 e54366f 22 0 2 3 65.536000 65.57698562 65 309766794 32 0 2 3 41 1276aa8a 20 0 2 3 74.175824 69.58332458 69 313169998 30 0 3 3 45 12aa984e 1e 0 3 3 74.250000 69.65290807 69 350527350 30 0 3 3 45 14e49f76 1e 0 3 3 77.760000 68.08255159 68 44319550 28 0 3 3 44 2a4433e 1c 0 3 3 106.250000 66.44777986 66 240399983 20 0 2 3 42 e54366f 14 0 2 3 125.000000 70.3564728 70 191379875 18 0 3 3 46 b6839a3 12 0 3 3 148.351648 74.22221288 74 119299633 16 0 3 4 4a 71c5e31 10 0 3 4 148.500000 74.29643527 74 159147475 16 0 3 4 4a 97c65d3 10 0 3 4 150.000000 65.66604128 65 357578187 14 0 2 3 41 155035cb e 0 2 3 155.520000 68.08255159 68 44319550 14 0 3 3 44 2a4433e e 0 3 3 156.250000 68.40212633 68 215889929 14 0 3 3 44 cde3809 e 0 3 3 212.500000 66.44777986 66 240399983 10 0 2 3 42 e54366f a 0 2 3 250.000000 78.17385866 78 93339658 10 0 4 4 4e 590400a a 0 4 4
SI514 16 rev. 1.0 6. determine values for lp1 and lp2 according to table 13: 7. write new lp1, lp2, m_frac, m_int, hs_div and ls_div register values (be sure to write m_int[8:3] (register 9) after writing to the m_frac registers (registers 5-8) 8. write fcal (register 132, bit 0) to a 1 (this bit auto-resets, so it will always read as 0). 9. enable the output: write oe register bit to a 1. the SI514 does not automatically detect large frequency changes. the user needs to assert the fcal register bit to initiate the calibration cycle requ ired to re-center the vco around the new frequency. large frequency changes are discontinuous and output may skip to intermediate fr equencies or generate glitches. resetting the oe bit before fcal will prevent intermediat e frequencies from appe aring on the output wh ile SI514 completes a calibration cycle and settles to f' center . settling time for large frequency changes is 10 msec maximum. example 2.2: the user has a part that is programmed with speed _grade_min = 20 and speed_grade_max = 250 that is programmed from the factory for f out = 50 mhz and wants to change to an sts-1 rate of 51.84 mhz. this represents a change of +36,800 ppm which exceeds 1000 ppm and therefore requires a large frequency change process. 1. write reg 132, bit 2 to a 0 to disable the output. 2. since 51.84 mhz is not in table 2.1, th e divider parameters must be calculated. 3. calculate ls_div by using eq 2.7: a. ls_div = 2080/(51.84 x 1022) = 0.039 b. since 0.039 < 1, use a divide-by-one (bypass), therefore ls_div = 0 4. calculate hs_div(min) by using eq 2.9: a. hs_div(min) = 2080/(51.84 x 1) = 40.123 b. since 40.123 > 40, use hs_div(min) = 42 = 0x2a 5. from eq 2.11: a. m = 1 x 42 x 51.84/31.98 = 68.08255159474 b. m_int = 68 = 0x44 c. m_frac = 0.08255259474 x 2 29 = 44,320,087 = 0x2a44557 6. from table 2.2: a. lp1 = 3 b. lp2 = 3 table 13. lp1, lp2 values fvco_max fvco_min m_max m_min lp1 lp2 2500000000.00000 2425467616.18572 78.173858662 75.843265046 4 4 2425467616.18572 2332545246.89005 75.843265046 72.937624981 3 4 2332545246.89005 2170155235.53450 72.937624981 67.859763463 3 3 2170155235.53450 2087014168.27005 67.859763463 65.259980246 2 3 2087014168.27005 2080000000.00000 65.259980246 65.040650407 2 2
SI514 rev. 1.0 17 7. write registers 0, 5-11: a. register 0 = 0x33 b. register 5 = 0x57 (m_frac[7:0]) c. register 6 = 0x45 (m_frac[15:8]) d. register 7 = 0xa4 (m_frac[23:16]) e. register 8 = 0x42 (m_int[2:0],m_frac[28:24]) f. register 9 = 0x05 (m_int[8:3]) g. register 10 = 0x2a h. register 11 = 0x00 8. calibrate the vco by writing register 132, bit 0 to a 1. 9. enable the output by writing register 132, bit 2 to a 1.
SI514 18 rev. 1.0 3. all-digital pll applications the SI514 uses a high resolution divider m that enable s fine frequency adjustments with resolution better than 0.026 parts per billion. fine frequency adjustments are useful when ma king frequency correcti ons that compensate for changing ambient conditions, long term aging or when locking the SI514 to an input clock reference. figure 3 shows a typical implementation using a system ic such as an fpga to control the output of the SI514 in a phase- locked application. refer to ?a n575: an introduction to fpga-bas ed adplls? for mo re information. figure 3. all-digital pll application using SI514 with dual cmos output since small frequency changes must be within 1000 ppm of the center frequency, hs_div and ls_div remain constant. the below expression can be used to calculate a new m 2 divider value based on a desired output frequency shift, where ? f out is in ppm. some systems, particularly those that use feedback co ntrol, can simplify the comp utation by implementing an approximate frequency change based on toggling a bit posi tion or adding/subtracting a bit to the existing m_frac value. since m ranges approximatel y 10% between 65.04065041 and 78 .17385866, the effe ct of changing m_frac by a single bit depends only s lightly on the absolute value of m. for m=71 near the midpoint of the range, toggling m_fr ac[0] changes the output fr equency by 0.026 ppb. each higher order bit doubles the influence such that toggling m_ frac[1] is 0.052 ppb, m_frac[2] is 0.1 ppb, etc. figure 4 shows this trend across multiple registers generalized to m_frac[n]. coarse changes greater than 1.7 ppm are possible but most applications require finer transitions . toggling each bit involves incrementing or decrementing the bit position. writing m_int[8:3] in register 9 completes the operation. figure 4. output frequency change when toggling m_frac[n], m=71 i 2 c control any frequency dspll clk_out fb SI514 fpga i 2 c master command conversion loop filter pd scl sda fin m 2 m 1 1 ? f out 10 6 ? ? ? ?? = m_int[8:0] = 000100111 m = 71.000000000000 m_frac[28:0] = 00000000000000000000000000000 m_frac[23:16] = 00000000 m_frac[15:8] = 00000000 m_frac[7:0] = 00000000 0.026ppb 6.7ppb 1.7ppm
SI514 rev. 1.0 19 4. user interface 4.1. register map table 14 displays the SI514 user register map. registers not shown are reserved. registers with reserved bits are read-modify-write. table 14. user register map address bit 76543210 0 lp1[3:0] lp2[3:0] 5 m_frac [7:0] 6 m_frac [15:8] 7 m_frac [23:16] 8 m_int [2:0] m_frac [28:24] 9 m_int [8:3] 10 hs_div [7:0] 11 ls_div [ 2:0] hs_div [9:8] 14 oe_state [1:0] 128 rst 132 oe fcal
SI514 20 rev. 1.0 4.2. register detailed description note: registers not shown are reserved. registers with reserved bits are read-modify-write. register 0. bit 76543210 name lp1[3:0] lp2[3:0] type r/w r/w default varies varies bit name function 7:4 lp1[3:0] sets loop compensation factor lp1. value depends on vco frequency. 3:0 lp2[3:0] sets loop compensation factor lp2. value depends on vco frequency. register 5. bit 76543210 name m_frac[7:0] type r/w default varies bit name function 7:0 m_frac[7:0] fractional part of feedback divider m that sets up the output frequency. frequency updates take effect when m_int[8:3] is written. register 6. bit 76543210 name m_frac[15:8] type r/w default varies bit name function 7:0 m_frac[15:8] fractional part of feedback divider m that sets up the output frequency. frequency updates take effect when m_int[8:3] is written.
SI514 rev. 1.0 21 register 7. bit 76543210 name m_frac[23:16] type r/w default varies bit name function 7:0 m_frac[23:16] fractional part of feedback divide r m that sets up the output frequency. frequency updates take effect when m_int[8:3] is written. register 8. bit 76543210 name m_int[2:0] m_frac[28:24] type r/w r/w default varies varies bit name function 7:5 m_int[2:0] integer part of feed back divider m that sets the out put frequency. frequency updates take effect when m_int[8:3] is written. 4:0 m_frac[28:24] fractional part of feedback divide r m that sets up the output frequency. frequency updates take effect when m_int[8:3] is written.
SI514 22 rev. 1.0 register 9. bit 76543210 name m_int[8:3] type r/w r/w r/w default varies bit name function 7:6 reserved 5:0 m_int[8:3] integer part of feed back divider m that sets the out put frequency. frequency updates take effect when m_int[8:3] is written. register 10. bit 76543210 name hs_div[7:0] type r/w default varies bit name function 7:0 hs_div[7:0] integer divider that divides vco fr equency and provides output to ls_div. follow the large frequency change procedure when u pdating. the allowed values are even num- bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ...., 1022). the decimal value represents the actual divide value (i.e. 12 means divide-by-12).
SI514 rev. 1.0 23 register 11. bit 76543210 name ls_div[2:0] hs_div[9:8] type r/w r/w r/w r/w r/w default varies varies bit name function 7 reserved 6:4 ls_div[2:0] last output divider stage. used du ring large frequency changes. to update, follow large frequency change procedure. ls _div value updates asynchronously. 000: divide-by-1 001: divide-by-2 010: divide-by-4 011: divide-by-8 100: divide-by-16 101: divide-by-32 all others reserved. 3:2 reserved 1:0 hs_div[9:8] integer divider that divides vco frequency and provides output to ls-div. follow the large frequency change procedure when u pdating. the allowed values are even num- bers in the range from 10 to 1022 (i.e., 10, 12, 14, 16, ..., 1022). the decimal value represents the actual divide value (i.e., 12 means divide-by-12). register 14. bit 76543210 name oe_state[1:0] type r/w r/w r/w r/w r/w r/w r/w default 0 0 bit name function 7:6 reserved 5:4 oe_state[1:0] sets logic state of output when output disabled. 00: high impedance 10: logic low when output disabled 01: logic high when output disabled 11: reserved 3:0 reserved
SI514 24 rev. 1.0 register 128. bit 76543210 name rst type r/wr/wr/wr/wr/wr/wr/wr/w default 0 bit name function 7rst global reset. resets all register values to default values. self-clearing. 6:0 reserved register 132. bit 76543210 name oe fcal type r/w r/w r/w r/w r/w r/w r/w r/w default 1 0 bit name function 7:3 reserved 2oe output enable. oe can stop in high, low or high impedance state. 1: output driver enabled. 0: output driver powered down. oe_state re gister determines output state when dis- abled. 1 reserved 0 fcal initiates frequency calibration cycl e. necessary when making large frequency changes. frequency calibration cycle takes 10 msec maximum. to prevent intermedi- ate frequencies on the output, set disable output using oe register. self-clearing.
SI514 rev. 1.0 25 4.3. i 2 c interface configuration and operation of the SI514 is controlle d by reading and writing to the ram space using the i 2 c interface. the device operates in sl ave mode with 7-bit addressing and can operate in standard-mode (100 kbps) or fast-mode (400 kbps). burst data transfer with auto address increments are also supported. the i 2 c bus consists of a bidirectional serial data line (sda) and a serial clock input (scl). both the sda and scl pins must be connected to the vdd supply via an external pull-up as recommended by the i 2 c specification. the SI514 7-bit i 2 c slave address is user-customized during the pa rt number configuration process. see "5. pin descriptions" on page 27 for more details. data is transferred msb first in 8-bit words as specified by the i 2 c specification. a write command consists of a 7- bit device (slave) address + a write bit, an 8-bit register address, and 8 bits of data as shown in figure 5. a write burst operation is also shown where every additi onal data word is written using an auto-incremented address. figure 5. i 2 c write operation a read operation is performed in two stages. a data writ e is used to set the register address, then a data read is performed to retrieve the data from the set address. a read burst operation is also supported. this is shown in figure 6. 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high) s ? start condition p ? stop condition from slave to master from master to slave write operation ? single byte s 0 a reg addr [7:0] slv addr [6:0] a data [7:0] p a write operation - burst (auto address increment) reg addr +1 s 0 a reg addr [7:0] slv addr [6:0] a data [7:0] a data [7:0] p a
SI514 26 rev. 1.0 figure 6. i 2 c read operation the timing specifications and timing diagram for the i 2 c bus is compatible with the i 2 c -bus standard. sda timeout is supported for compatib ility with smbus interfaces. the i 2 c bus can be operated at a bus voltage of 1.71 to 3.63 v and is 3.3 v tolerant. 1 ? read 0 ? write a ? acknowledge (sda low) n ? not acknowledge (sda high) s ? start condition p ? stop condition from slave to master from master to slave read operation ? single byte s 0 a reg addr [7:0] slv addr [6:0] a p read operation - burst (auto address increment) reg addr +1 s 1 a slv addr [6:0] data [7:0] p n s 0 a reg addr [7:0] slv addr [6:0] a p s 1 a slv addr [6:0] data [7:0] a p n data [7:0]
SI514 rev. 1.0 27 5. pin descriptions 5.1. dual cmos (1:2 fanout buffer) dual cmos output format ordering options support either complementary or in-phase output signals. this feature enables replacement of multiple xos with a single SI514 device. figure 7. integrated 1:2 cmos buffer supports complementary or in-phase outputs table 15. SI514 pin descriptions pin name function 1 sda i 2 c serial data. 2 scl i 2 c serial clock. 3 gnd electrical and case ground. 4 clk+ clock output. 5 clk- complementary clock output (lvpecl, lvds, hcsl, and complementary dual cmos formats). clock output for in-phase dual cmos format. no connect (n/c) for sing le-ended cmos format. 6 v dd power supply voltage. 1 2 3 6 5 4 gnd scl v dd clk+ clk? sda ~ ~ complementary outputs in-phase outputs
SI514 28 rev. 1.0 6. ordering information the SI514 supports a wide va riety of options including st artup frequency, stability, outp ut format, and vdd. specific device configurations are programmed into the SI514 at time of shipment. configurations can be specified using the part number config uration chart below. silicon l abs provides a web br owser-based pa rt number configuration utility to simplify this proce ss. refer to www.silabs.com/v cxopartnumber to access this tool. the SI514 xo series is supplied in industry-standard, rohs-compliant, 3.2 x 5.0 mm and 5 x 7 mm packages. tape and reel packaging is an ordering option. figure 8. part number convention example orderable part number: 5 14ecb000107aag supports 2.5 v lvpec l, 30 ppm total stability, user programmable output frequency range from 100 khz to 170 mhz, 5x7 mm package and ?40 to 85 c temperature range. the frequency code desi gnates 10 mhz startup with i 2 c address of 0x55. refer to www.silabs.com/vcxo lookup to look up the attrib utes of any silicon labs or derable xo/vcxo part number. note: cmos and dual cmos maximum frequency is 212.5 mhz. x x 514 x xxxxxx x 3 rd option code: frequency grade 1 st option code: output format 2 nd option code: frequency stability total temperature a 100ppm 50ppm b 50ppm 25ppm c 30ppm 20ppm package option dimensions a 5 x 7 mm b 3.2 x 5 mm vdd output format a 3.3v lvpecl b3.3v lvds c3.3v cmos d 3.3v hcsl e 2.5v lvpecl f2.5v lvds g2.5v cmos h 2.5v hcsl j1.8v lvds k1.8v cmos l 1.8v hcsl m 3.3v dual cmos (in-phase) n 3.3v dual cmos (complementary) p 2.5v dual cmos (in-phase) q 2.5v dual cmos (complementary) r 1.8v dual cmos (in-phase) s 1.8v dual cmos (complementary) series output format package 514 lvpecl, lvds, hcsl, cmos, dual cmos 6-pin code description xxxxxx the SI514 supports a u ser-defined start-up frequency which must be in the same range as specified by the frequency grade code. a user-defined, 7-bit i 2 c address is supported. each unique start-up frequency/i 2 c address combination is assigned a 6-digit code by: www.silabs.com/vcxopartnumber . 6-digit frequenc y and default i 2 c address code agr a = revision: a g = temp range: -40c to 85c r = tape & reel; blank = trays. cmos (mhz) lvpecl, lvds, hcsl (mhz) a 0.1 to 212.5 0.1 to 250 b 0.1 to 170 0.1 to 170 c 0.1 to 125 0.1 to 125
SI514 rev. 1.0 29 7. package outline di agram: 5 x 7 mm, 6-pin figure 9 illustrates the 5 x 7 mm, 6-pin pa ckage details for the SI514. table 16 lists the values for the dimensions shown in the illustration. figure 9. SI514 outline diagram table 16. package diagram dimensions (mm) dimension min nom max a 1.50 1.65 1.80 b 1.30 1.40 1.50 c 0.50 0.60 0.70 d 5.00 bsc d1 4.30 4.40 4.50 e 2.54 bsc e 7.00 bsc e1 6.10 6.20 6.30 h 0.55 0.65 0.75 l 1.17 1.27 1.37 l1 0.05 0.10 0.15 p1.80?2.60 r0.70 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI514 30 rev. 1.0 8. pcb land pattern: 5 x 7 mm, 6-pin figure 10 illustrates the 5 x 7 m m, 6-pin pcb land pattern for the si51 4. table 17 lists th e values for the dimensions shown in the illustration. figure 10. SI514 pcb land pattern table 17. pcb land pattern dimensions (mm) dimension (mm) c1 4.20 e2.54 x1 1.55 y1 1.95 notes: general 1. all dimensions shown are in m illimeters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
SI514 rev. 1.0 31 9. package outline diag ram: 3.2 x 5.0 mm, 6-pin figure 11 illustrates the 3.2 x 5 mm pack age details for the SI514. table 18 lis ts the values for the dimensions shown in the illustration. figure 11. SI514 outline diagram table 18. package diagram dimensions (mm) dimension min nom max a1.061.171.28 b0.540.640.74 c0.350.450.55 d 3.20 bsc d1 2.55 2.60 2.65 e 1.27 bsc e 5.00 bsc e1 4.35 4.40 4.45 h0.450.550.65 l0.901.001.10 l1 0.05 0.10 0.15 p1.171.271.37 r0.32 ref aaa 0.15 bbb 0.15 ccc 0.10 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
SI514 32 rev. 1.0 10. pcb land pattern: 3.2 x 5.0 mm, 6-pin figure 12 illustrates the 3.2 x 5.0 mm pcb land pattern for the SI514. ta ble 19 lists the values for the dimensions shown in the illustration. figure 12. SI514 recommended pcb land pattern table 19. pcb land pattern dimensions (mm) dimension (mm) c1 2.60 e1.27 x1 0.80 y1 1.70 notes: general 1. all dimensions shown are in milli meters (mm) unless otherwise noted. 2. dimensioning and tolerancing is per th e ansi y14.5m-1994 specification. 3. this land pattern design is based on the ipc-7351 guidelines. 4. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. solder mask design 5. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 6. a stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 7. the stencil thickness should be 0.125 mm (5 mils). 8. the ratio of stencil aperture to land pad size should be 1:1. card assembly 9. a no-clean, type-3 solder paste is recommended. 10. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
SI514 rev. 1.0 33 11. top marking use the part number config uration utility located at: www.silabs.com/vcxopartnumber to cross-reference the mark code to a specific device configuration. 11.1. SI514 top marking 11.2. top marking explanation mark method: laser line 1 marking: 4 = SI514 ccccc = mark code 4ccccc line 2 marking: tttttt = assembly manufacturing code tttttt line 3 marking: pin 1 indicator. circle with 0.5 mm diameter; left-justified yy = year. ww = work week. characters correspond to the year and work week of package assembly. yyww 4ccccc ttt t t t yyww
SI514 34 rev. 1.0 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated table 1 on page 4. ?? updates to supply current typical and maximum values for cmos, lvds, lvpecl and hcsl. ?? cmos frequency test condition corrected to 100 mhz. ?? updates to oe vih minimum and vil maximum values. ? updated table 2 on page 4. ?? dual cmos nominal frequency maximum added. ?? total stability footnotes clarified for 10 year aging at 40 c. ?? disable time maximum values updated. ?? enable time parameter added. ? updated table 3 on page 5. ?? cmos output rise / fall time typical and maximum values updated. ?? lvpecl/hcsl output rise / fall time maximum value updated. ?? lvpecl output swing maximum value updated. ?? lvds output common mode typical and maximum values updated. ?? hcsl output swing maximum value updated. ?? duty cycle minimum and maxi mum values tightened to 48/52%. ? updated table 5 on page 7. ?? phase jitter test condition and maximum value updated. ?? phase noise typical values updated. ?? additive rms jitter due to external power supply noise typical values updated. ?? footnote 3 updated limi ting the vdd to 2.5/3.3v ? added tables 6, 7, 8 for lvds, hcsl, cmos, and dual cmos operations. ? moved absolute maximum ratings table. ? added note to figure 8 clarifying cmos and dual cmos maximum frequency. ? updated figure 9 outline diagram to correct pinout. ? updated ?11. top marking? section and moved to page 33.
SI514 rev. 1.0 35 n otes :
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